TCL Commands and Packages

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Tcl Command Tcl Package Package Version
add_new_cell chip_planner 2.0
add_new_io chip_planner 2.0
add_row_to_table report 2.1
add_to_collection sta 1.0
add_usage chip_planner 2.0
all_clocks sdc 1.5
all_inputs sdc 1.5
all_outputs sdc 1.5
all_registers sdc 1.5
analyze_files interactive_synthesis 1.0
apply_command chip_planner 2.0
apply_setting external_memif_toolkit 1.0
assignment_group project 6.0
auto_partition_design incremental_compilation 1.1
begin_logic_analyzer_interface_control logic_analyzer_interface 1.0
begin_memory_edit insystem_memory_edit 1.0
blueprint__initialize periph 1.0
blueprint__shutdown periph 1.0
boundary_optimizations incremental_compilation 1.1
calibrate_termination external_memif_toolkit 1.0
change_bank_to_output_pin logic_analyzer_interface 1.0
check fif 1.0
check_netlist_and_save chip_planner 2.0
check_node chip_planner 2.0
check_rtl_connections interactive_synthesis 1.0
check_timing sta 1.0
checksum misc 1.0
clear_ip_generation_dirs ipgen 1.0
close_chip_planner chip_planner 2.0
close_device jtag 1.0
close_session stp 1.0
compute_pll iptclgen 1.0
configure_driver external_memif_toolkit 1.0
connect_chain chip_planner 2.0
convert_signal_probes chip_planner 2.0
create_base_clock project 5.0
create_clock sdc 1.5
create_connection_report external_memif_toolkit 1.0
create_generated_clock sdc 1.5
create_migrated_script chip_planner 2.0
create_partition incremental_compilation 1.1
create_relative_clock project 5.0
create_report_histogram sta 1.0
create_report_panel report 2.1
create_revision project 6.0
create_slack_histogram sta 1.0
create_timing_netlist sta 1.0
create_timing_summary sta 1.0
create_toolkit_report external_memif_toolkit 1.0
delete_all_logiclock incremental_compilation 1.1
delete_all_partitions incremental_compilation 1.1
delete_logiclock incremental_compilation 1.1
delete_netlist flow 1.1
delete_partition incremental_compilation 1.1
delete_report_panel report 2.1
delete_revision project 6.0
delete_sp chip_planner 2.0
delete_sta_collection sta 1.0
delete_timing_netlist sta 1.0
derive_clock_uncertainty sdc_ext 1.0
derive_clocks sdc 1.5
derive_pll_clocks sdc_ext 1.0
design__commit_design design 1.0
design__create_assignment design 1.0
design__delete_assignments design 1.0
design__disable_assignments design 1.0
design__enable_assignments design 1.0
design__export_design design 1.0
design__export_partition design 1.0
design__get_assignment_info design 1.0
design__get_assignment_names design 1.0
design__get_assignments design 1.0
design__get_entity_names design 1.0
design__get_instances design 1.0
design__import_design design 1.0
design__import_partition design 1.0
design__list_valid_snapshot_names design 1.0
design__load_design design 1.0
design__report_assignments design 1.0
design__set_assignment_info design 1.0
design_has_ace_support chip_planner 2.0
design_has_encrypted_ip chip_planner 2.0
device_dr_shift jtag 1.0
device_ir_shift jtag 1.0
device_lock jtag 1.0
device_run_test_idle jtag 1.0
device_unlock jtag 1.0
device_virtual_dr_shift jtag 1.0
device_virtual_ir_shift jtag 1.0
disable_natural_bus_naming misc 1.0
disable_sp chip_planner 2.0
discard_all_changes chip_planner 2.0
discard_node_changes chip_planner 2.0
dissolve_rtl_partition interactive_synthesis 1.0
driver_margining external_memif_toolkit 1.0
dump fif 1.0
dump_cram_frame fif 1.0
dump_mem fif 1.0
dump_pr_bitstream fif 1.0
elaborate interactive_synthesis 1.0
enable_ccpp_removal sta 1.0
enable_natural_bus_naming misc 1.0
enable_sdc_extension_collections sta 1.0
enable_sp chip_planner 2.0
end_insystem_source_probe insystem_source_probe 1.0
end_logic_analyzer_interface_control logic_analyzer_interface 1.0
end_memory_edit insystem_memory_edit 1.0
escape_brackets misc 1.0
establish_connection external_memif_toolkit 1.0
execute_assignment_batch project 6.0
execute_flow flow 1.1
execute_module flow 1.1
export_assignments project 6.0
export_data_log stp 1.0
export_database database_manager 1.0
export_partition incremental_compilation 1.1
export_persona incremental_compilation 1.1
export_stack_to chip_planner 2.0
foreach_in_collection misc 1.0
generate fif 1.0
generate_bottom_up_scripts database_manager 1.0
generate_eye_diagram external_memif_toolkit 1.0
generate_ip_file ipgen 1.0
generate_project_ip_files ipgen 1.0
generate_qxp_report incremental_compilation 1.1
generate_vhdl_simgen_model iptclgen 1.0
get_active_clocks sdc_ext 1.0
get_all_assignment_names project 6.0
get_all_assignments project 6.0
get_all_global_assignments project 6.0
get_all_instance_assignments project 6.0
get_all_parameters project 6.0
get_all_quartus_defaults project 6.0
get_all_user_option_names project 6.0
get_assignment names 1.0
get_assignment_groups sdc_ext 1.0
get_assignment_info project 6.0
get_assignment_name_info project 6.0
get_available_operating_conditions sta 1.0
get_back_annotation_assignments backannotate 1.1
get_cell_info sta 1.0
get_cells sdc 1.5
get_clock_domain_info sta 1.0
get_clock_fmax_info sta 1.0
get_clock_info sta 1.0
get_clocks sdc 1.5
get_collection_size misc 1.0
get_connection_commands external_memif_toolkit 1.0
get_connection_info external_memif_toolkit 1.0
get_connection_interfaces external_memif_toolkit 1.0
get_connection_report_info external_memif_toolkit 1.0
get_connection_report_types external_memif_toolkit 1.0
get_connection_types external_memif_toolkit 1.0
get_connections external_memif_toolkit 1.0
get_current_project project 6.0
get_current_revision project 6.0
get_current_state_of_output_pin logic_analyzer_interface 1.0
get_database_version project 6.0
get_datasheet sta 1.0
get_default_sdc_file_names sta 1.0
get_device_names jtag 1.0
get_edge_info sta 1.0
get_edge_slacks sta 1.0
get_editable_mem_instances insystem_memory_edit 1.0
get_entities interactive_synthesis 1.0
get_entity_instances sta 1.0
get_environment_info misc 1.0
get_exact_placement_changed_nodes incremental_compilation 1.1
get_family_list device 1.0
get_fanins sdc_ext 1.0
get_fanouts sdc_ext 1.0
get_fitter_resource_usage report 2.1
get_flow_templates flow 1.1
get_frame_count fif 1.0
get_frame_size fif 1.0
get_global_assignment project 6.0
get_hardware_names jtag 1.0
get_info_parameters chip_planner 2.0
get_instance_assignment project 6.0
get_insystem_source_probe_instance_info insystem_source_probe 1.0
get_iports chip_planner 2.0
get_keepers sdc_ext 1.0
get_location_assignment project 6.0
get_logiclock incremental_compilation 1.1
get_logiclock_contents incremental_compilation 1.1
get_min_pulse_width sta 1.0
get_name_info project 6.0
get_names project 6.0
get_net_info sta 1.0
get_nets sdc 1.5
get_node_by_name chip_planner 2.0
get_node_info sta 1.0
get_node_loc chip_planner 2.0
get_nodes sdc_ext 1.0
get_nodes_changed_before_cloud_expansion incremental_compilation 1.1
get_nodes_changed_in_cloud_expansion incremental_compilation 1.1
get_number_of_columns report 2.1
get_number_of_rows report 2.1
get_object_info sta 1.0
get_operating_conditions sta 1.0
get_operating_conditions_info sta 1.0
get_oports chip_planner 2.0
get_output_persona_filename incremental_compilation 1.1
get_parameter project 6.0
get_parameter_settings synthesis_report 1.0
get_parameter_settings_info synthesis_report 1.0
get_part_info device 1.0
get_part_list device 1.0
get_partition incremental_compilation 1.1
get_partition_file_list incremental_compilation 1.1
get_partition_info sta 1.0
get_partitions sdc_ext 1.0
get_path sta 1.0
get_path_info sta 1.0
get_pin_info sta 1.0
get_pins sdc 1.5
get_placement_changed_nodes incremental_compilation 1.1
get_placement_partially_preserved_nodes incremental_compilation 1.1
get_point_info sta 1.0
get_port_by_type chip_planner 2.0
get_port_info sta 1.0
get_ports sdc 1.5
get_project_directory project 6.0
get_project_ip_files ipgen 1.0
get_project_revisions project 6.0
get_project_settings project 1.0
get_register_info sta 1.0
get_registers sdc_ext 1.0
get_report_panel_column_index report 2.1
get_report_panel_data report 2.1
get_report_panel_id report 2.1
get_report_panel_names report 2.1
get_report_panel_row report 2.1
get_report_panel_row_index report 2.1
get_routing_changed_nodes incremental_compilation 1.1
get_rtl_cell_info rtl 1.0
get_rtl_cells rtl 1.0
get_rtl_fanins rtl 1.0
get_rtl_fanouts rtl 1.0
get_rtl_partition_name interactive_synthesis 1.0
get_rtl_partitions interactive_synthesis 1.0
get_rtl_pin_info rtl 1.0
get_rtl_pins rtl 1.0
get_sensitive_location fif 1.0
get_setting_types external_memif_toolkit 1.0
get_source_assignment_info synthesis_report 1.0
get_source_assignments synthesis_report 1.0
get_sp_pin_list chip_planner 2.0
get_stack chip_planner 2.0
get_tile_power_setting chip_planner 2.0
get_timing_paths sta 1.0
get_toolkit_report_types external_memif_toolkit 1.0
get_top_level_entity project 6.0
get_user_option project 6.0
help_arg_examples help 1.0
import_database database_manager 1.0
import_partition incremental_compilation 1.1
import_persona incremental_compilation 1.1
init_tk misc 1.0
initialize_connections external_memif_toolkit 1.0
is_database_version_compatible project 6.0
is_fitter_in_qhd_mode project 6.0
is_post_route tdc 1.0
is_project_open project 6.0
link_project_to_device external_memif_toolkit 1.0
link_rtl_design interactive_synthesis 1.0
list_sps chip_planner 2.0
load misc 1.0
load_package misc 1.0
load_report report 2.1
load_rtl_netlist rtl 1.0
locate sta 1.0
logiclock_back_annotate backannotate 1.1
make_ape_connection chip_planner 2.0
make_input_port chip_planner 2.0
make_output_port chip_planner 2.0
make_sp chip_planner 2.0
merge_partitions incremental_compilation 1.1
netlist_exists flow 1.1
open_device jtag 1.0
open_session stp 1.0
parse_hdl iptclgen 1.0
parse_tcl iptclgen 1.0
partition_delete_netlists incremental_compilation 1.1
partition_netlist_exists incremental_compilation 1.1
periph__check_plan periph 1.0
periph__get_cell_info periph 1.0
periph__get_cells periph 1.0
periph__get_location_info periph 1.0
periph__get_placement_info periph 1.0
periph__get_placements periph 1.0
periph__load_floorplan periph 1.0
periph__place_cells periph 1.0
periph__remove_invalid_reports periph 1.0
periph__report_all periph 1.0
periph__report_cell_connectivity periph 1.0
periph__report_cell_placement_reasons periph 1.0
periph__report_cells periph 1.0
periph__report_clocks periph 1.0
periph__report_legal_cell_locations periph 1.0
periph__report_location_types periph 1.0
periph__report_locations periph 1.0
periph__report_regions periph 1.0
periph__report_summary periph 1.0
periph__reset_plan periph 1.0
periph__save_floorplan periph 1.0
periph__set_clock_type periph 1.0
periph__undo_last_placement periph 1.0
periph__unplace_cells periph 1.0
periph__update_plan periph 1.0
periph__write_plan periph 1.0
post_message misc 1.0
print_ipxact interactive_synthesis 1.0
project_archive project 6.0
project_clean project 6.0
project_close project 6.0
project_exists project 6.0
project_new project 6.0
project_open project 6.0
project_restore project 6.0
project_settings_exist project 1.0
qerror misc 1.0
qexec misc 1.0
qexit misc 1.0
qshm_connect_to_quartus qshm 1.0
qshm_disconnect_from_quartus qshm 1.0
qshm_dispose_client qshm 1.0
qshm_get_hub_key_prefix qshm 1.0
qshm_get_parent_hub_key qshm 1.0
qshm_obtain_client qshm 1.0
qshm_send_request qshm 1.0
qshm_send_server_state_query qshm 1.0
qshm_set_context qshm 1.0
query_collection sta 1.0
read_content_from_memory insystem_memory_edit 1.0
read_netlist chip_planner 2.0
read_probe_data insystem_source_probe 1.0
read_sdc sta 1.0
read_setting external_memif_toolkit 1.0
read_source_data insystem_source_probe 1.0
read_xml_report report 2.1
refresh_report_window report 2.1
register_delete_timing_netlist_callback sta 1.0
reindex_connections external_memif_toolkit 1.0
remove_all_global_assignments project 6.0
remove_all_instance_assignments project 6.0
remove_all_parameters project 6.0
remove_annotated_delay sdc_ext 1.0
remove_ape_connection chip_planner 2.0
remove_chain chip_planner 2.0
remove_clock sdc_ext 1.0
remove_clock_groups sdc 1.5
remove_clock_latency sdc 1.5
remove_clock_uncertainty sdc 1.5
remove_disable_timing sdc 1.5
remove_from_collection sta 1.0
remove_input_delay sdc 1.5
remove_input_port chip_planner 2.0
remove_old_cell chip_planner 2.0
remove_output_delay sdc 1.5
remove_output_port chip_planner 2.0
remove_usage chip_planner 2.0
report_advanced_io_timing sta 1.0
report_atom_node_summary rtl 1.0
report_bottleneck sta 1.0
report_cdc_viewer sta 1.0
report_clock_fmax_summary sta 1.0
report_clock_transfers sta 1.0
report_clocks sta 1.0
report_datasheet sta 1.0
report_ddr sta 1.0
report_device_info device 1.0
report_exceptions sta 1.0
report_family_info device 1.0
report_ini_usage sta 1.0
report_max_skew sta 1.0
report_metastability sta 1.0
report_min_pulse_width sta 1.0
report_net_delay sta 1.0
report_net_timing sta 1.0
report_parameter_settings synthesis_report 1.0
report_part_info device 1.0
report_partitions sta 1.0
report_path sta 1.0
report_removed_registers synthesis_report 1.0
report_resource_utilization synthesis_report 1.0
report_rskm sta 1.0
report_rtl_assignments interactive_synthesis 1.0
report_rtl_parameters interactive_synthesis 1.0
report_rtl_pin_summary rtl 1.0
report_rtl_stats interactive_synthesis 1.0
report_sdc sta 1.0
report_skew sta 1.0
report_source_assignments synthesis_report 1.0
report_tccs sta 1.0
report_timing sta 1.0
report_timing_tree sta 1.0
report_ucp sta 1.0
reset_design sdc 1.5
reset_rtl_design interactive_synthesis 1.0
reset_tg2 external_memif_toolkit 1.0
reset_timing_derate sdc_ext 1.0
resolve_file_path project 6.0
revision_exists project 6.0
routing_path chip_planner 2.0
rtm_in_post_fit_retimer rtm 1.0
rtm_retime rtm 1.0
run stp 1.0
run_connection_command external_memif_toolkit 1.0
run_multiple_end stp 1.0
run_multiple_start stp 1.0
save_content_from_memory_to_file insystem_memory_edit 1.0
save_report_database report 2.1
save_rtl_design interactive_synthesis 1.0
set_active_clocks sdc_ext 1.0
set_active_interface external_memif_toolkit 1.0
set_annotated_delay sdc_ext 1.0
set_assignment names 1.0
set_batch_mode chip_planner 2.0
set_clock_groups sdc 1.5
set_clock_latency sdc 1.5
set_clock_uncertainty sdc 1.5
set_current_revision project 6.0
set_disable_timing sdc 1.5
set_false_path sdc 1.5
set_global_assignment project 6.0
set_high_effort_fmax_optimization_assignments project 6.0
set_input_delay sdc 1.5
set_input_transition sdc 1.5
set_instance_assignment project 6.0
set_io_assignment project 6.0
set_location_assignment project 6.0
set_logiclock incremental_compilation 1.1
set_logiclock_contents incremental_compilation 1.1
set_max_delay sdc 1.5
set_max_skew sdc_ext 1.0
set_min_delay sdc 1.5
set_multicycle_assignment project 5.0
set_multicycle_path sdc 1.5
set_net_delay sdc_ext 1.0
set_node_info chip_planner 2.0
set_operating_conditions sta 1.0
set_output_delay sdc 1.5
set_parameter project 6.0
set_partition incremental_compilation 1.1
set_port_info chip_planner 2.0
set_power_file_assignment project 6.0
set_project_settings project 1.0
set_scc_mode sdc_ext 1.0
set_stress_pattern external_memif_toolkit 1.0
set_tile_power_setting chip_planner 2.0
set_time_format sdc_ext 1.0
set_timing_cut_assignment project 5.0
set_timing_derate sdc_ext 1.0
set_user_option project 6.0
setup fif 1.0
split_partition incremental_compilation 1.1
start_insystem_source_probe insystem_source_probe 1.0
stop stp 1.0
stopwatch misc 1.0
synthesize interactive_synthesis 1.0
terminate fif 1.0
terminate_connection external_memif_toolkit 1.0
terminate_connections external_memif_toolkit 1.0
test_assignment_trait project 6.0
timegroup project 4.0
timing_netlist_exist sta 1.0
tristate_output_pin logic_analyzer_interface 1.0
undo_command chip_planner 2.0
uniquify interactive_synthesis 1.0
unlink_project_from_device external_memif_toolkit 1.0
unload_report report 2.1
unload_rtl_netlist rtl 1.0
update_content_to_memory_from_file insystem_memory_edit 1.0
update_node_loc chip_planner 2.0
update_timing_netlist sta 1.0
use_timequest_style_escaping sta 1.0
write_connection_target_report external_memif_toolkit 1.0
write_content_to_memory insystem_memory_edit 1.0
write_flow_finished flow 1.1
write_flow_started flow 1.1
write_flow_template flow 1.1
write_report_panel report 2.1
write_rtl_report interactive_synthesis 1.0
write_sdc sta 1.0
write_source_data insystem_source_probe 1.0
write_xml_report report 2.1