Generate HDL (Generate Menu) (Qsys Pro)
The Quartus® Prime software uses Qsys Pro-generated synthesis HDL files during compilation. You can generate simulation HDL files, which can include simulation-only features targeted towards your simulator. You can generate simulation files as Verilog or VHDL, for use in your simulation environment. The Generation dialog box allows you to choose options to generate Qsys Pro design files for synthesis and simulation.