Debug Tools Setting Summary Reports

Synthesis generates the following reports based on the settings of the debug tools that communicate with Intel devices via the JTAG server.

Signal Tap Logic Analyzer Settings Report:

Reports the following information about all the Signal Tap instances created based on the Signal Tap Logic Analyzer settings selected in the Signal Tap Logic Analyzer Settings page. This report is created during Synthesis.

  • Instance Index shows the order assigned to the instance by the Intel® Quartus® Prime software.
  • Instance Name shows the name of the instance you specify.
  • Trigger Input Width shows the width of the node, in bits, that connects to the triggering logic.
  • Data Input Width shows the width of the node, in bits, that connects to the acquisition memory.
  • Sample Depth shows the number of samples that can be acquired.
  • Segments shows the number of segments being analyzed.
  • Trigger Flow Control shows the type of trigger flow control in use.
  • Trigger Conditions shows the number of sequential trigger condition levels.
  • Advanced Trigger Conditions shows the number of advanced trigger condition levels set among all trigger levels.
  • Trigger In Used shows whether the trigger-in setting is turned on or off.
  • Trigger Out Used shows whether the trigger-out setting is turned on or off.
  • Power-Up Trigger Enabled shows whether the power-up trigger is turned on or off.

Signal Tap Logic Analyzer Instances Instantiated in Design Settings Report:

Reports information about instances instantiated in a design with the sld_signaltap Intel® FPGA IP. This report is created during Analysis & Synthesis.

  • Instance Index: Order assigned to the instance by the Intel® Quartus® Prime software.
  • Instance Name: Name of the instance as modified by the user.
  • Trigger Input Width: Width of the acq_trigger_in, in bits, that connects to the triggering logic.
  • Data Input Width: Width of the acq_data_in, in bits, that connects to the acquisition memory.
  • Sample Depth: Number of samples that can be acquired.
  • Trigger Levels: Number of sequential trigger condition levels.
  • Advanced Trigger Levels: Number of advanced trigger condition levels in a series you set for sampling.
  • Trigger In Used: Shows whether the trigger_in is connected.
  • Trigger Out Used: Shows whether the trigger_out is connected.
  • Hierarchy Location: Hierarchy level in which the sld_signaltap Intel® FPGA IP is instantiated.

In-System Memory Content Editor Settings Report:

Reports information about the size of the RAM block, where it is located, and whether you can write to it at run-time. The information is generated during Analysis & Synthesis. You can use the In-System Memory Content Editor by using the IP Catalog to set up and instantiate lpm_rom, lpm_ram_dq, altsyncram, and lpm_constant Intel® FPGA IP, or by instantiating these Intel® FPGA IP directly in the design, using the lpm_hint Intel® FPGA IP parameter.

  • Instance Index: Order assigned to the instance by the Intel® Quartus® Prime software.
  • Instance ID: User-specified ID of the memory block instance.
  • Width: Width of the memory word in bits.
  • Depth: Number of memory words for the memory block instance.
  • Mode: Shows whether the mode is either read/write or read-only, which is determined by the RAM block type.
  • Hierarchy location: Location in the design where the Intel® FPGA IP is instantiated.

Logic Analyzer Interface Settings Report:

Reports the results of performing a compilation with the Logic Analyzer Interface enabled.

  • Instance Index: Order assigned to the instance by the Intel® Quartus® Prime software.
  • Instance Name: Name of the instance.
  • Bank Count: Number of banks that can be connected to the output pins.
  • Pin Count: Number of output pins created to be probed using an external logic analyzer.
  • Output/Capture Mode: Shows whether the output pins are configured in either Registered/State or Combinational/Timing mode.
  • Power-up State: Shows whether the output pins are tri-stated or connected to bank 0 after the Intel device is configured.

Virtual JTAG Settings Report:

Reports information about instances of the sld_virtual_jtag Intel® FPGA IP present in the design:

  • Instance Index: Order assigned to the instance by the Intel® Quartus® Prime software.
  • Auto Index: Shows whether the Auto Index feature is enabled.
  • Index Reassigned: Shows whether the index was reassigned by the Intel® Quartus® Prime software due to a conflict in the design.
  • Address: Instance address.
  • USER1 DR length: Length of the data register targeting the USR1 JTAG instruction for the instance.
  • VIR capture instruction: Virtual instruction register capture instruction value for the instance.
  • IR Width: Width of the instruction register in bits.
  • Hierarchy Location: Hierarchy level in which the sld_virtual_jtag Intel® FPGA IP is instantiated.