Allows you to specify the number of processors the Quartus II software can use at once to run parallel executables, which reduces execution time.

When you run any parallel executable with parallel compilation enabled, you can find information about the average processor use, the maximum number of processors used, and the amount of time the processors used in the Parallel Compilation Report.

Parallel compilation is set to Use global compilation setting by default.

• Use global parallel compilation setting— Sets Parallel compilation to the setting specified under Parallel compilation in the Processing page of the Options dialog box.

• Use all available processors— Specifies that the Quartus II software uses all available processors to run parallel executables.

• Maximum processors allowed— Specifies the number of processors parallel executables can use on a single machine at the same time. For example, if you have a quad-core processor machine and want to leave one processor free for other tasks, you would specify 3 as the setting of this option. Setting this option to 1 effectively disables parallel compilation.

Currently, only some Quartus II software executables, such as quartus_fit, are parallel, so when you set this option to a value greater than 1, a portion of the Quartus II software processing still occupies only one processor.

This option is available for all Altera device families supported by the Quartus II software except MAX 3000 and MAX 7000 family devices.

Directs the Compiler to perform a smart compilation, which allows future recompilations to run faster.

During a recompilation after a smart compilation, the Compiler determines which Compiler modules are required to process the current design based on the changes made to the design since the smart compilation, and then skips any modules that are not required. If you make any changes to the logic of a design, the Compiler uses all the modules during processing.

When the Compiler skips a module during a recompilation, the Messages window and the Messages sections of the Compilation Report window do not redisplay any messages that the skipped module issued during the smart compilation.

Allows you to save disk space and reduces compilation time by specifying that the Compiler not preserve node name synonyms in the database. However, the Compiler still preserves all user-defined node names.

Runs I/O assignment analysis before design fitting. Turning on this option allows you to see potential problems with design layout before starting a long fitting process.

Directs the Compiler to run the Assembler during compilation.

Allows the RTL Viewer to process the schematic during design compilation. Turning on this option also allows you to open the RTL Viewer after the Analysis & Synthesis portion of design compilation completes, rather than waiting for the full compilation to complete.

Directs the Compiler Database Interface to save synthesis results for the current design's top-level entity as an atom-based netlist in Verilog Quartus Mapping File (.vqm) format during a full compilation.

The File name box specifies the name of the Verilog Quartus Mapping File that the Compiler Database Interface generates when saving synthesis results. By default, the Quartus II software places the Verilog Quartus Mapping File in the atom_netlists directory under the current project directory. You can direct the Quartus II software to place this file in a different directory by specifying the directory path in the File name box. However, the Quartus II software cannot place the Verilog Quartus Mapping File in the same directory as the current project.

The Start VQM Writer command allows you to save synthesis results in a Verilog Quartus Mapping File without running a full compilation (for example, after performing just Analysis & Synthesis on a design). You can specify the directory path and name of the Verilog Quartus Mapping File by turning on Save a node-level netlist into a persistent source file and specifying a directory path and file name in the File name box before choosing the command. If you turn off Save a node-level netlist of the entire design into a persistent source file before pointing to Start and then clicking Start VQM Writer, the command saves the Verilog Quartus Mapping File in the atom_netlists directory with a default name.

If you are already compiling only from EDIF Input Files (.edf) or Verilog Quartus Mapping Files, which are atom-based netlists, you do not need to save synthesis results with the Quartus II software. You may need to save synthesis results if you are using a combination of atom-based netlists and other source files, such as files generated by the MegaWizard Plug-In Manager.

Allows you to export the current project as version-compatible database files during a full compilation.

The Export version-compatible database option is turned off by default.

The Export directory box specifies the directory in which the version-compatible database files are stored.

Allows you to specify the directory where output files are saved.

Opens the More Compilation Process Settings dialog box, which allows you to specify logic option and compilation process settings for the current design.