Set Input Delay Dialog Box (set_input_delay)


You access this dialog box by clicking Set Input Delay on the Constraints menu in the TimeQuest Timing Analyzer, or with the set_input_delay Synopsys Design Constraints (SDC) command.

 

Specifies the data required time at the specified input ports relative to the clock. The Clock name must refer to an actual clock name in the design.

You can specify input delays relative to the rising edge (default) or falling edge (-clock_fall) of the clock. The TimeQuest analyzer uses the maximum input delay (-max) for clock setup checks or recovery checks, and uses the minimum input delay (-min) for clock hold checks or removal checks. If you specify only the minimum or maximum delay for a given port, the same value is used for both. You can specify separate rising (-rise) and falling (-fall) arrival times at the port. If you specify only the rise or only the fall value for a given port, the specified value is used for both rise and fall.

By default, the TimeQuest analyzer removes any other input delays to the port except for those input delays with the same clock name (-clock), falling clock edge (-clock_fall), and reference pin (-reference pin) specification. To specify multiple input delays relative to different clocks, turn on the Add delay (-add_delay) option.

 

The following sections provide more information about specifying options for this constraint:

 

ExpandClock name (-clock):

ExpandUse falling clock edge (-clock_fall):

ExpandInput delay options (-min, -max, -rise, -fall):

ExpandDelay value:

ExpandAdd delay (-add_delay):

ExpandTargets:

ExpandSDC command:

 

 

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