The Hierarchy tab provides a visual representation of the project hierarchy, specific resource usage information, and device and device family information. The resource usage columns are populated with data after design compilation, and the data is accurate until you update the design, for example, by changing the device or device family, assigning logic options, changing the top-level design entity, changing the design source code, or making other changes that can reallocate the use of device resources. Inaccurate data is displayed in red.
The top-level design entity of the project is displayed on the Hierarchy tab. After you compile a design, if the top-level design entity contains any lower-level entities, a + icon appears beside the top-level design entity indicating that you can expand that entity to view the lower-level entities.
The Hierarchy tab displays updates when you compile a design. The lower-level entities in the Hierarchy tab follow the naming format <entity>:<instance>.
You can select multiple entities on the Hierarchy tab for further processing, such as copying to the clipboard for reporting, or moving as a group to a single location, for example, to the same LogicLock® Plusregion.
If an entity contains parameter settings, a tooltip window containing the settings is displayed when you hold the pointer over the entity. Viewing the parameter data directly from the Project Navigator can be useful for VHDL diagrams, because you can quickly view the parameter information and verify whether all parameters correctly passed.