SRFFE primitive allows you to specify an
SR-type flipflop with clock enable.
ENA(clock enable) input is high, the flipflop passes a signal that is dependent on the
Q. When the
ENAinput is low, the state of
Qis maintained, regardless of the
For devices that do not support clock enable, logic synthesis generates logic equations containing flipflops with clock enables. These logic equations correctly emulate the logic specified in the project.