BIDIR or INOUT Primitive/Port
|AHDL Syntax:||Verilog HDL Example Instantiation:||VHDL Syntax:||Source:||Destination:|
Device I/O pin
TRI is disabled, external input is allowed. If
TRI is enabled and an external signal is applied,
signal contention is possible and could damage the device.
In a Block Design File (.bdf) Definition, you can use the Pin Properties dialog box to specify pin properties for this primitive, such as the pin name and default value.
- Only the pin assignments of the top-level entity are used during compilation.
- For information about Quartus® Prime primitive instantiation, go to Using a Quartus® Prime Logic Function.