Creating a Design for Use with the Synplify Software

You can create VerilogHDL design files with the Quartus® Prime Text Editor or another standard text editor for use with the Synopsys Synplify software.

To create a Verilog HDL or VHDL design for use with the Synplify software:

  1. If you have not already done so, perform Setting Up the Synplify Working Environment.
  2. Enter a VHDL or Verilog HDL design in the Quartus® Prime Text Editor or another standard text editor and save it in your working directory. Only describe the design with Verilog HDL or VHDL; the Synplify software cannot synthesize Block Design File (.bdf) Definition or other proprietary Intel formats.

    When connecting ports in the Verilog Design File (.v) Definition , make sure you connect ports by name instead of by order. When generating Verilog Output File (.vo) Definition from imported VQM Files for simulation in other EDA simulation tools, the Quartus® Prime software does not retain the order of ports.

  3. To use megafunctions in the design, use the IP Catalog to generate and instantiate a megafunction variation. You can use the MegaWizard Plug-In Manager to create LVDS or RAM Definition functions.
  4. Instantiate any Quartus® Prime"“supported logic functions in the Verilog HDL design. You can enter the following functions:
    • Parameterized and non-parameterized megafunctions. The Quartus® Prime software also supports all functions in the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions.
    • Buffer primitives, including lcell, soft, global, carry, and cascade. The Synopsys altera.v and altera.vhd libraries provide synthesis support for these functions.
    • MegaCore functions offered by Intel or by members of the Altera Megafunction Partners Program (AMPP). The OpenCore feature in the Quartus® Prime software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.
  5. If your VHDL design uses functions from the altera.vhd library, add the following library and use clauses to the top of a file that instantiates the macrofunction(s):
    library altera; use altera.maxplus2.all;
  6. For each Quartus® Prime"“supported logic function, include a syn_black_box synthesis directive. You can omit this step for functions from the altera.v and altera.vhd libraries.
  7. For any parameterized function, declare all parameters used in the function, their types, and their values. The following examples show a VerilogHDL and VHDL file that instantiates the lpm_ram_dq function.
    • Example of a Verilog Design File with LPM Function Instantiation
    • Example of a VHDL Design File with LPM Function Instantiation
  8. To continue with the Synplify design flow, set up a project with the Synplify software.