Example of Performing a Timing Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software
To perform a timing simulation on your design using the ModelSim software once you compile your design in the Quartus® Prime software, you can create a script that performs the following steps:
- Compiles the <device family> _atoms.v library.
- Compiles the Verilog Output File (.vo) Definitionthe Quartus® Prime software generates during compilation. In this example, the Verilog Output File name is pllsource.vo.
- Compiles the test bench file. In this example, the test bench file name is plltest.v.
You can simulate the sample design in the ModelSim software by using the commands shown in the following sample script:
vlib work # Create working directory vlog /quartus/eda/sim_lib/apex20ke_atoms.v # Read the simulation library # /quartus/ is the path to Quartus® Prime vlog pllsource.vo # Compile Quartus® Prime output netlist vlog plltest.v # Compile test fixture vsim -t ps work.plltest # Simulate plltest with resolution in ps add wave /plltest/* # Add the port signals to the waveform view run 1000 ns # Run the simulation for 1000 ns