Assigning Design Constraints with the Precision RTL Synthesis Software
You can also set design constraints in the Precision RTL Synthesis software. The Precision RTL Synthesis software then creates a <design name>_constraints.sdc Synopsys Design Constraint File in the current project directory. To set design constraints in the Precision RTL Synthesis software user interface:
- If you have not already done so, set up a project with the Precision RTL Synthesis software.
- To create clock(s) for the design and set clock attributes:
- In the Design Hierarchy window, click the + icon to expand the Clocks folder.
- To create a clock and set clock constraints for a specific clock, right-click on the clock, and click Set Clock Constraints.
- To set additional attributes for a specific clock, right-click on the clock, and click Set Attributes.
- To set timing and mapping constraints on ports:
- In the Design Hierarchy window, expand the Ports folder.
- Expand the Inputs or Outputs folder.
- Right-click a specific port and click Set Input Constraints or Set Output Constraints. The Port Constraints dialog box appears.
- Use the Port Constraints dialog box to set timing and mapping constraints, including pin numbers, I/O standards, and I/O pads.
- You can also right-click on a specific port and click Force Register into I/O to force registers to be moved into I/O elements during synthesis.
- To disable I/O pad insertion on I/O pins in the design during synthesis:
- Click Set Options. The Synthesis Options dialog box appears.
- Select Optimization.
- Turn off Add IO Pads.
- Click OK.
- To continue with the Precision RTL Synthesis design flow, generate EDIF Netlist Files with the Precision RTL Synthesis software.