Performing a Simulation of a VHDL Design with the Active-HDL Software

You can run the Aldec Active-HDL software to perform RTL functional simulation, post-synthesis simulation, and gate-level timing simulation of a VHDL design that contains Intel-specific components from the Active-HDL interface. You can use simulation libraries provided with the Quartus® Primesoftware, or download simulation libraries directly from Aldec.

Note: For more information about using EDA simulators, refer to Aldec Active-HDL and Riviera-PRO Support in the Quartus® Prime Handbook.