Create VHDL Component Declaration Files for Current File Command (File Menu)
Creates VHDL Component Declaration File (.cmp) Definition that contain the declaration of a component, which can be used in a VHDL Design File (.vhd) Definition. The declaration file generated represents the VHDL component of the entities in the current Text Design File (.tdf) DefinitionVHDL Design File,Verilog Design File (.v) DefinitionBlock Design File (.bdf) DefinitionCusp Design File (.cpp), or DSP Builder File (.mdl). The Quartus® Prime software creates a .cmp file for each declared entity in the current file. Each created file has the same name as its corresponding entity.