Set Clock Uncertainty Dialog Box (set_clock_uncertainty)

You access this dialog box by clicking Constraints > Set Clock Uncertainty in the Timing Analyzer, or with the set_clock_uncertainty Synopsys® Design Constraints (SDC) command.

Allows you to specify the expected clock setup or hold uncertainty associated with jitter, skew, and a guard band when performing setup and hold checks for clocks or clock-to-clock transfers. You can specify separate clock uncertainty for setup (-setup) and hold (-hold). The Timing Analyzer subtracts the setup uncertainty from the data required time Definition for each applicable path, and adds the hold uncertainty to the data required time for each applicable path.

The following sections provide more information about specifying options for this constraint:

From clock (-from):

Allows you to specify a valid source clock.

To clock (-to):

Allows you to specify a valid destination clock.


Specifies the clock uncertainty value.

Analysis type(-setup, -hold):

Allows you to specify whether you want to perform clock setup or clock hold analysis. The following options are available:

  • Setup (-setup)— Allows you to specify a clock uncertainty value for clock setup or recovery checks.
  • Hold (-hold)— Allows you to specify a clock uncertainty value for clock hold or removal checks. If the hold check is performed on the same edge, the user defined set_clock_uncertainty -hold is ignored by the Timing Analyzer. You can use -enable_same_physical_edge option to account for this hold uncertainty.

SDC command:

Displays and allows you to enter SDC commands for the options you specify in this dialog box.