About the SignalTap II Logic Analyzer

 


The SignalTap II Logic Analyzer Editor allows you to debug your design in real-time and at high-speed while performing an analysis in the Quartus II software. With the SignalTap II Logic Analyzer Editor you create one SignalTap II File (.stp) that contains all SignalTap II Logic Analyzer configuration data. When you run a SignalTap II analysis you capture data and save it to the SignalTap II File, which is then included in your design. Each design can have only one SignalTap II File for each device you are programming. You can make changes to the parameters and settings in that SignalTap II File with the SignalTap II Logic Analyzer Editor, which is the main window you see when you first open the SignalTap II Logic Analyzer. After capturing the data and saving it to a SignalTap II File, you can view the data you capture in a waveform. The SignalTap II Logic Analyzer Editor provides the control to select specific nodes and choose when and how much data to capture from those nodes. You can then route the data to device memory, or route the trigger condition to an I/O pin to use the SignalTap II Logic Analyzer in conjunction with an external logic analyzer or oscilloscope. You monitor the memory resources that the embedded logic of the SignalTap II Logic Analyzer uses on your device to determine possible changes to your design.

When you set up the SignalTap II Logic Analyzer, you create a SignalTap II File that contains the data you capture. Your design can have more than one instance of the embedded logic that comprises the SignalTap II Logic Analyzer, and each instance can be modified so that you can select, modify, or delete specific nodes in your design. You capture data according to the trigger conditions you set, which are logic events that occur in input nodes. The SignalTap II File contains the trigger settings that you make. You can specify an order of these events with the Trigger Flow Control.

If you want to make multiple configurations of the embedded logic that comprises the SignalTap II Logic Analyzer for performing triggering under various conditions, you can attach a SRAM Object File (.sof), which contains configuration data, to an open SignalTap II File.

To run an analysis you must select an instance in the SignalTap II Logic Analyzer Editor. The data you capture when running the analysis displays in the Wave Display pane. You can then view, edit, or print the waveforms, or export the data into another format for further analysis.

After you make changes to settings in the SignalTap II Logic Analyzer Editor, you must recompile the design. You can recompile the design without a SignalTap II File if you use the SignalTap II Logic Analyzer megafunction. A SignalTap II Logic Analyzer megafunction is an IP core that you can instantiate into your design by creating an instance in the Instance Manager pane, or with the IP Catalog.

 

ExpandSignalTap II Flow Diagram:

ExpandSignalTap II Procedure Flow:

ExpandSignalTap II Incremental Compilation:

ExpandSignalTap II Rapid Recompile:

 About Triggering

 About Data Acquisition with the SignalTap II Logic Analyzer

 About SignalTap II Storage Qualification

 

Related Help Topics

Following are Help topics related to the SignalTap II Logic Analyzer:

ExpandAbout:

ExpandCommands:

ExpandDialog Boxes:

ExpandTabs:

ExpandExamples:

ExpandProcedures:

 

Scripting Information

Executable: quartus_stp

 

You can edit a SignalTap II instance in the project with the quartus_stp executable before running Analysis & Synthesis. The quartus_stp also provides Tcl commands for you to script the SignalTap II Logic Analyzer acquisition.

 

Scripting Information

Executable: quartus_stpw

 

When you open the Programmer, you can run SignalTap II Logic Analyzer editor with the quartus_stpw executable.

 

More information is available on the SignalTap II Logic Analyzer on the Altera website.

 

For more information about the SignalTap II Logic Analyzer, refer to the Altera Training page of the Altera website.

 

 

Rate This Page