About Simulating Designs

 


Simulation verifies design behavior before device programming. The Quartus II software supports RTL- and gate-level design simulation in various third-party simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, running your simulator, and interpreting the results. You can integrate your supported simulator into the Quartus II design flow using the NativeLink feature. The Quartus II design flow also supports various custom and scripted simulation flows.

The Quartus II software supports both Verilog HDL and VHDL simulation of encrypted and unencrypted Altera IP cores. If your design includes Altera IP cores, you must compile any corresponding IP simulation models in your simulator with the rest of your design and testbench. The Quartus II software generates and copies the simulation models for IP cores to your project directory.

 

ExpandSimulation Flow Diagram:

ExpandSupported Simulators:

 

 

Refer to Simulating Altera Designs in the Quartus II Handbook for more details.

 

 

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