Implementing Inferred RAM (Verilog HDL)

 


The Quartus II software can infer RAM from a suitable description in a Verilog Design File (.v). You can implement RAM in a Verilog HDL design as an alternative to implementing RAM using an Altera-provided megafunction (which is described in Implementing CAM, RAM and ROM). RAM inference is controlled by the Auto RAM Replacement logic option, which is turned on by default.

The Quartus II software recognizes byte-enabled, mixed-width dual-port, single-port, simple dual-port, and true dual-port RAM. RAM is inferred only for target families that have appropriate RAM blocks. No RAM is inferred for devices without RAM blocks. Similarly, if the Verilog Design File describes an asynchronous RAM, no RAM is inferred when the target family has RAM blocks that do not support an asynchronous mode.

 

Note: Although Stratix III now support the use of asynchronous clear signals on input registers, if you use asynchronous clear signals in Verilog Design Files, the signals are emulated with extra logic around the RAM, which might affect performance.

 

The example below shows ram_single.v, a Verilog Design File that implements a 128 x 8-bit synchronous single-port RAM with common read and write addresses:

module ram_single(q, a, d, we, clk);
   output[7:0] q;
   input [7:0] d;
   input [6:0] a;
   input we, clk;
   reg [7:0] mem [127:0];
    always @(posedge clk) begin
        if (we)
            mem[a] <= d;
        q <= mem[a];
   end
endmodule
 

The example below shows ram_dual.v, a Verilog Design File that implements a 128 x 8-bit simple dual-port RAM with separate read and write clocks. When the Quartus II software infers a RAM block for a memory with separate read and write clocks, the functionality of the design will change slightly. The behavior when reading and writing to the same address will be different. When the functionality of the design changes, the Quartus II software issues a warning message to alert the user and describe the changes.


module ram_dual(q, addr_in, addr_out, d, we, clk1, clk2);
   output[7:0] q;
   input [7:0] d;
   input [6:0] addr_in;
   input [6:0] addr_out;
   input we, clk1, clk2;
 
   reg [6:0] addr_out_reg;
   reg [7:0] q;
   reg [7:0] mem [127:0];
 
   always @(posedge clk1) begin
      if (we)
         mem[addr_in] <= d;
   end
 
   always @(posedge clk2) begin
      q <= mem[addr_out_reg];
      addr_out_reg <= addr_out;
   end
        
endmodule

Other examples of inferred RAM are available by clicking Insert Template on the Edit menu with a file open in the Quartus II Text Editor. In the Insert Template dialog box, click the + icon to expand the navigation tree until you see the type of RAM you would like to infer.

 

 

Rate This Page