logic element

 


The smallest unit of logic located in a LAB of all Altera devices supported by the Quartus II software except MAX 3000 and MAX 7000 devices. A logic element is also generally known as a logic cell.

In supported device family devices, a logic element consists of a four-input LUT, a programmable register, and a carry chain. Supported device family logic elements also supports a dynamic single-bit addition or subtraction mode that is selectable by a LAB-wide control signal. Each logic element drives the local, row, column, carry chain, register chain, and direct link interconnects.

Each programmable register of a supported device family logic element can be configured for D, T, JK, or SR operation, or bypassed entirely for pure combinational logic. The register's clock, clear, clock enable, preset, asynchronous load, and asynchronous data control can be driven by general-purpose I/O pins or any internal logic. The register's clock and clear can also be driven by global signals.

You can assign a logic function to a specific logic element in supported device family devices. You can also assign a logic function to a Custom region to make sure the function is implemented in a logic element in that Custom region.

Logic elements have "numbers" of the following format for the following devices:

 

Device Family

Format for Logic Element "Numbers"

Variable and Number Descriptions

Arria series,
Cyclone series, and
Stratix series

LC_X<number>_Y<number>_N<number>

X<number>

The column number that contains the LAB that contains the logic element.

Y<number>

The row number that contains the LAB that contains the logic element.

N<number>

The logic element number ranging from 0 to 10.

 

Note: A fast input-type logic cell that is associated with an I/O pin in a MAX 7000 device is also known as an I/O cell or I/O element.

 

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