Specifying the Initial Contents of Inferred Memories in VHDL Designs

 


Integrated Synthesis supports several methods for specifying the initial contents of inferred memories in your VHDL design.

  1. Use the ram_init_file synthesis attribute to associate a MIF with a variable that represents your RAM.

  2. Assign an initial value to your RAM variable.

// Initialize in the declaration
type memory_t is array(0 to 15) of integer;
signal ram : memory_t  := ( others => '1' );

 

// Initialize with a file
signal ram : memory_t;
attribute ram_init_file of ram : signal is "ram.mif";

 

 

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