Performing a Timing Simulation with the ModelSim Software

You can perform a timing simulation of a Verilog HDL or VHDL design with the Mentor Graphics ModelSim PE or SE software with the ModelSim interface or with command-line commands.

If you have not already done so, compile libraries and design files with the ModelSim software.
If the design contains device-wide reset or device power-up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
On the Simulate menu, click Simulate. The Simulate dialog box appears.
If you are simulating a Verilog HDL design, click the Verilog tab. Under Pulse Options, type 0 in the Error Limit and Rejection Limit boxes.
If you are simulating a VHDL design, to specify the Standard Delay Format Output File (.sdo):
1. Click the SDF tab.
2. Click Add.
3. In the Add SDF Entry dialog box, click Browse. The Select SDF File dialog box appears.
4. In the Files of type list, select All Files (*.*).
5. Select the Standard Delay Output File.
6. Click Open.
7. Click OK.

Note: If you are using a test bench file to provide simulation stimuli to the design, in the Apply to region box, specify the path to the design instance in the test bench, starting from the top-level design file.

Click the Design tab.
In the Name list, expand the work directory and select the design entity that corresponds to the Standard Delay Output File.
Click Add.
Select the top-level Verilog HDL or VHDL Output File or test bench.
Click Add.
If you are simulating high-speed circuits (including designs that use HSSI, LVDS, or PLLs):
1. Click the Other tab.
2. In the Other options box type +transport_int_delays and +transport_path_delays.
3. Click OK.
Click Load.
To direct the ModelSim software to generate a Value Change Dump File (.vcd) that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer, type the following command at the ModelSim prompt:

source <test bench or design instance name>_dump_all_vcd_nodes.tcl

The Tcl Script File (.tcl) directs the ModelSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.
Perform the timing simulation in the ModelSim software.

To perform a timing simulation of a Verilog HDL or VHDL design with the Mentor Graphics ModelSim (OEM) software with command-line commands:

Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the ModelSim-Altera or ModelSim PE or SE main window into a text file and name the file with a .do extension (that is, <file name>.do). Use this script to recompile the libraries if you update them.

To run a macro script:

From the Mentor Graphics ModelSim main window, chose Execute Macro.
In the Execute Do File dialog box, locate your ModelSim macro file (.do).
Click Open.

1. If you have not already done so, compile libraries and design files with the ModelSim software.
2. If your design contains device-wide reset or device power up signals, and if you have not already done so, set up the signals in the Verilog Output File or set up the signals in the VHDL Output File.
3. To load the design with minimum, typical, or maximum timing values, type the following commands at the ModelSim prompt:
4. vsim -t ps -sdf(min | typ | max) +transport_int_delays +transport_path_delays /=<design name>.sdo work.<top-level design entity>

1. To direct the ModelSim software to generate a Value Change Dump File (.vcd) that you can then use to perform power analysis in the Quartus II PowerPlay Power Analyzer, type the following command at the ModelSim prompt:
  
  source <test bench or design instance name>_dump_all_vcd_nodes.tcl
  
  The Tcl Script File (.tcl) directs the ModelSim software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.
2. Perform the timing simulation in the ModelSim software.