Performing a Timing Simulation with the ModelSim Software



Important: Altera recommends that you set Time scale settings to picoseconds (ps) in the interface or with command-line commands when performing timing simulations of designs with RAM.


You can perform a timing simulation of a Verilog HDL or VHDL design with the Mentor Graphics ModelSim PE or SE software with the ModelSim interface or with command-line commands.



  • You can use the EDA Simulation Library Compiler in the Quartus II software to quickly compile simulation libraries before beginning your simulation.

  • You do not need to compile Altera simulation libraries if using the ModelSim-Altera simulator.


click to expandTo perform a timing simulation with the ModelSim interface:

click to expandTo perform a timing simulation with command-line commands:


If you want to perform power analysis, perform power analysis with the PowerPlay Power Analyzer.